3. 강의목표
To learn how to design complex digital systems using a hardware description language (Verilog) and to learn how to design, construct and test a computer using an FPGA.
4. 강의선수/수강필수사항
At least one previous introductory "digital logic design" class is required for this course (non-POSTECH courses are also acceptable; email me for special permission if required).
5. 성적평가
Quizzes: 40%; Final Exam: 20%; Online Textbook Assignments: 5%; PLMS (MOOC) quizzes: 5%; Verilog Programming Assignments: 30%
6. 강의교재
| 도서명 |
저자명 |
출판사 |
출판년도 |
ISBN |
|
Computer Organization and Design – Interactive Version (ARM) - zybooks edition
|
D. A. Patterson and J. L. Hennessy
|
Elsevier
|
2017
|
9780128017333
|
7. 참고문헌 및 자료
S. Lee, Advanced Digital Logic Design: Using Verilog, State Machines, and Synthesis for FPGAs, Thomson, 2006.
8. 강의진도계획
1. Digital Logic Review and Introduction to Computer Technology and Terminology
2. Instructions
3. Arithmetic for Computers
4. The Processor
5. Memory Hierarchy
6. Parallel Processors from Client to Cloud
7. Design Examples using Verilog HDL mixed in with the above sections
(Fast Arithmetic Units (Adders/Subtractors, Multipliers/Dividers),
Standard Input/Output Interface Design,
Computer Design - Pipelined RISC ARM Architecture)
9. 수업운영
- online textbook
- all students, including graduate students, should take this course on a Grade (G) basis instead of Pass/Fail
10. 학습법 소개 및 기타사항
This semester, we will be using the INTERACTIVE ONLINE version of the Computer Organization and Design textbook, authored by Patterson and Hennessy, as the required textbook for this class. The required book can be obtained by going to learn.zybooks.com and entering the code POSTECHEECE375LeeFall2024
11. 장애학생에 대한 학습지원 사항
- 수강 관련: 문자 통역(청각), 교과목 보조(발달), 노트필기(전 유형) 등
- 시험 관련: 시험시간 연장(필요시 전 유형), 시험지 확대 복사(시각) 등
- 기타 추가 요청사항 발생 시 장애학생지원센터(279-2434)로 요청