2025-Fall VLSI Ana.&Design Software (EECE667-01) The course syllabus

1.Course Information

Course No. EECE667 Section 01 Credit 3.00
Category Major elective Course Type prerequisites
Postechian Core Competence
Hours MON, WED / 14:00 ~ 15:15 / Elec Bldg[105]Lecture Room Grading Scale G

2. Instructor Information

Kang Seokhyeong Name Kang Seokhyeong Department Dept. of Electrical Eng.
Email address shkang@postech.ac.kr Homepage soc.postech.ac.kr
Office CAD & SOC DESIGN LAB. Office Phone 054-279-2379
Office Hours

3. Course Objectives

This course aims to convey a knowledge of VLSI design automation. From the Week 1 to Week 11, students will learn the latest algorithms used in the modern physical design (place-and-route) and power optimization as well as their theoretical background. In the Week 12, AI application to VLSI design, which is one of the most promising topic in the industry, will be covered. Lastly, from the Week 13 to Week 14, students will have the experience of running the modern VLSI design flow with commercial VLSI design software. They will also have the experience of implementing their own VLSI design algorithms based on the knowledges covered in this lecture.

Key Items:introduction to EDA, circuit theory, numerical techniques, graph theory & data structure, physical design, and real world of EDA software

본 강의는 초집적회로의 설계 자동화에 대해 학습하는 과목입니다. 1주차부터 11주차까지 학생들은 초집적회로의 배치 및 배선, 소모 전력 최적화 등에 필요한 이론적 배경 및 실제 반도체 설계 현장에서 사용되는 최신 알고리즘들을 학습하게 되고, 또한 12주차에는 현재 산업계에서 큰 주목을 받고 있는 인공 지능을 활용한 반도체 설계에 대해서 소개할 계획입니다. 마지막으로 13주차부터 14주차에는 상용 반도체 설계 소프트웨어를 사용하여 디지털 집적회로가 만들어지는 과정을 실제로 체험해보고, 학습한 내용들을 바탕으로 본인만의 반도체 설계 알고리즘을 직접 만들어보는 실무 프로젝트 경험을 제공할 계획입니다.

4. Prerequisites & require

Prerequisite: VLSI System Design Note: There will be software development projects. Due to NDA restrictions on commercial PDK libraries, this course is not open to international exchange students.

5. Grading

Attendance(10%) / Homework(20%) / Midterm(20%) / Final Exam(30%) / Term project(20%)

6. Course Materials

Title Author Publisher Publication
Year/Edition
ISBN

7. Course References

VLSI Physical Design: From Graph Partitioning to Timing Closure, Andrew Kahng, 2011
EDA general: Mark Birnbaum, Essential Electronic Design Automation (EDA), P-H, 2004
Circuit analysis: Computer Aided Analysis of Electronic Circuits, Chua
Inside EDA: Dirk Jansen et al., The Electronic Design Automation Handbook, Kluwer Academic Publishers 2003

8. Course Plan

1. Introduction to modern VLSI design flow
2. Overview on the delay and power
3. Delay modeling, STA, timing optimization
4. Clock Distribution
5. Floorplanning and Partitioning
6. Placement
7. Routing and power distribution
8. Cost, packaging and 3D integration
9. Verification and DFT
10. Signoff
11. Low-power implementation
12. Emerging technology: AI-EDA
13. Project Presentation and demos
14. Project Presentation and demos
15. Summary

9. Course Operation

기본적으로 대면강의 (필요 시 온라인 진행)

Online (Zoom) class

https://us02web.zoom.us/j/83409652339?pwd=Ny9DTUl2bjVmMWdBSmxTcFBBUXRpUT09

회의 ID: 834 0965 2339
암호: postech667

10. How to Teach & Remark

향후 산업현장에서의 활용도를 높이기 위한 반도체 설계 자동화 분야의 상용 툴을 과제에서 사용함. 아울러 설계 자동화 알고리즘 구현에는 파이썬 등의 프로그래밍 언어를 활용함.

11. Supports for Students with a Disability

- Taking Course: interpreting services (for hearing impairment), Mobility and preferential seating assistances (for developmental disability), Note taking(for all kinds of disabilities) and etc.

- Taking Exam: Extended exam period (for all kinds of disabilities, if needed), Magnified exam papers (for sight disability), and etc.

- Please contact Center for Students with Disabilities (279-2434) for additional assistance