반도체의 고속 신호처리, 저전력, 신호동기화 등의 역할에 필요한 칩 내부 외부의 배선 회로의 설계 최적화에 필요한 기술을 학습을 목표로 한다. 패키지 성분을 포함한 집적된 소자들간의 최적 데이터통신 위한 IO 회로 설계에 대한 개념을 습득한 후, 프로젝트기반 사례연구로 직렬링크, 병렬링크, 메모리인터페이스 및 부가회로 등의 Chip-to-chip IO 회로설계 능력을 습득한다.

This course focuses on design optimization technologies for on-chip and off-chip interconnects, essential for high-speed signal processing, low-power operation, and signal synchronization in semiconductors. Students will first learn IO circuit design concepts for optimal data communication (including package components), then develop chip-to-chip IO design skills through project-based case studies covering serial links, parallel links, memory interfaces, and supporting circuits.

- 선수강: 전자회로2 수준의 회로 지식
- 필수사항: Term project 설계 수행을 위해 본인 소속 연구실의 CAD server (Virtuso 및 hspice/spectre) 환경을 갖추고 사용이 가능한 학생. 본 수업은 별도의 CAD Tool 지원을 하지 않음.

- Prerequisite: "Electronic Circuits II" or equivalent knowledge.
- Important Requirements: Students are required to have access to their affiliated Lab's CAD server environment (e.g., Cadence Virtuoso, HSpice/Spectre) to complete the design term project.
Please note that CAD tools access will not be supported by this course.

Design of Integrated Circuits for Optical Communications, Behzad Razavi, Wiley.
High-Bandwidth Memory Interface, Chulwoo Kim, Springer

Week 1 : Overview & Qualifying HW
Week 2 : Transmission lines and channel characteristics
Week 3 : Basic IO Building Blocks (Transmitter & Receiver)
Week 4 : Advanced IO Building Blocks (Equalization)
Week 5-6 : Topic presentation (1)
Week 7-8 : Clock generation (PLL & DLL)
Week 9 :　Serial IO system (CDR)
Week 10 : Mid term project presentation
Week 11 : Memory IO system (Parallel)
Week 12-13 : Topic presentation (2)
Week 14 : Jitter and Noise
Week 15-16 : Final term project presentation